Static Timing Analysis

Project : Echo
Build Time : 04/27/18 11:44:45
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 56.386 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 38.242 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 56.386 MHz 17.735 23.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.472
macrocell6 U(0,2) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(0,2) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 82.406 MHz 12.135 29.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.472
macrocell21 U(0,2) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 82.406 MHz 12.135 29.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.472
macrocell24 U(0,2) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 89.135 MHz 11.219 30.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.556
macrocell18 U(0,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 89.135 MHz 11.219 30.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.556
macrocell23 U(0,1) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 89.238 MHz 11.206 30.461
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.543
macrocell22 U(1,1) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 90.367 MHz 11.066 30.601
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.403
macrocell15 U(0,1) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 38.242 MHz 26.149 13015.518
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 9.600
macrocell2 U(2,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 6.819
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 38.967 MHz 25.663 13016.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 8.054
macrocell2 U(2,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 6.819
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.341 MHz 23.073 13018.594
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 5.464
macrocell2 U(2,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 6.819
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.852 MHz 22.804 13018.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 5.195
macrocell2 U(2,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 6.819
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 55.002 MHz 18.181 13023.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,1) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 5.906
macrocell5 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 56.215 MHz 17.789 13023.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 5.514
macrocell5 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.787 MHz 16.726 13024.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 4.451
macrocell5 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxSts\/status_0 60.849 MHz 16.434 13025.233
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_status_0\/main_2 10.141
macrocell3 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.253
statusicell1 U(2,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 61.188 MHz 16.343 13025.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 10.143
datapathcell1 U(2,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 61.501 MHz 16.260 13025.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.924
macrocell7 U(1,1) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 5.906
statusicell2 U(0,2) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.403
macrocell15 U(0,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 7.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.543
macrocell22 U(1,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.709
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.556
macrocell18 U(0,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.709
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.556
macrocell23 U(0,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 8.625
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.472
macrocell21 U(0,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 8.625
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.472
macrocell24 U(0,2) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.153
Route 1 Net_51 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.472
macrocell6 U(0,2) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(0,2) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.182
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,1) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.932
statusicell2 U(0,2) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 3.249
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.629
macrocell21 U(0,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 3.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.631
macrocell21 U(0,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_3\/main_7 3.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_3\/main_7 2.796
macrocell17 U(1,2) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 3.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 2.798
macrocell17 U(1,2) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 3.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.803
macrocell16 U(1,2) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 3.434
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.814
macrocell16 U(1,2) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 3.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,2) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.921
macrocell19 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 3.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 1.510
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.247
macrocell9 U(2,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell9 U(2,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.531
macrocell9 U(2,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_7 Pin_8(0)_PAD 23.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_18 \Control_Reg_1:Sync:ctrl_reg\/control_7 Pin_8(0)/pin_input 6.171
iocell8 P3[7] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 15.161
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_1(0)_PAD 22.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_11 \Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_1(0)/pin_input 6.159
iocell1 P3[0] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 14.620
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_4(0)_PAD 22.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_14 \Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_4(0)/pin_input 6.140
iocell4 P3[3] 1 Pin_4(0) Pin_4(0)/pin_input Pin_4(0)/pad_out 14.591
Route 1 Pin_4(0)_PAD Pin_4(0)/pad_out Pin_4(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_6(0)_PAD 22.761
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_16 \Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_6(0)/pin_input 5.373
iocell6 P3[5] 1 Pin_6(0) Pin_6(0)/pin_input Pin_6(0)/pad_out 15.338
Route 1 Pin_6(0)_PAD Pin_6(0)/pad_out Pin_6(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_2(0)_PAD 22.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_12 \Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_2(0)/pin_input 5.377
iocell2 P3[1] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 14.979
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_3(0)_PAD 22.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_13 \Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_3(0)/pin_input 5.334
iocell3 P3[2] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 14.995
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_5(0)_PAD 22.346
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_15 \Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_5(0)/pin_input 5.309
iocell5 P3[4] 1 Pin_5(0) Pin_5(0)/pin_input Pin_5(0)/pad_out 14.987
Route 1 Pin_5(0)_PAD Pin_5(0)/pad_out Pin_5(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_6 Pin_7(0)_PAD 22.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_17 \Control_Reg_1:Sync:ctrl_reg\/control_6 Pin_7(0)/pin_input 5.365
iocell7 P3[6] 1 Pin_7(0) Pin_7(0)/pin_input Pin_7(0)/pad_out 14.591
Route 1 Pin_7(0)_PAD Pin_7(0)/pad_out Pin_7(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_46/main_0 2.532
macrocell1 U(2,0) 1 Net_46 Net_46/main_0 Net_46/q 3.350
Route 1 Net_46 Net_46/q Tx_1(0)/pin_input 7.371
iocell10 P1[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.071
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000