Static Timing Analysis

Project : 16C450_Replacement_Final
Build Time : 08/11/17 19:21:24
Device : CY8C5888LTI-LP097
Temperature : 0C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 89.759 MHz
UART_1_Clock CyMASTER_CLK 76.800 kHz 76.800 kHz 58.976 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 89.759 MHz 11.141 9.692
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 3.542
macrocell24 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 2.345
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.114
datapathcell3 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 2.430
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 110.473 MHz 9.052 11.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 5.885
macrocell41 U(2,3) 1 \UART_1:BUART:rx_status_3\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 149.054 MHz 6.709 14.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.542
macrocell39 U(2,5) 1 \UART_1:BUART:pollcount_1\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 149.054 MHz 6.709 14.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.542
macrocell40 U(2,5) 1 \UART_1:BUART:pollcount_0\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 159.872 MHz 6.255 14.578
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.088
macrocell33 U(2,5) 1 \UART_1:BUART:rx_state_0\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 159.872 MHz 6.255 14.578
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.088
macrocell36 U(2,5) 1 \UART_1:BUART:rx_state_2\ SETUP 2.457
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 159.872 MHz 6.255 14.578
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.710
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.088
macrocell42 U(2,5) 1 \UART_1:BUART:rx_last\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 13020.8ns(76.8 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 58.976 MHz 16.956 13003.877
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,5) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 0.875
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 6.511
macrocell23 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 3.465
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.090 MHz 15.603 13005.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,5) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 0.875
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 5.158
macrocell23 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 3.465
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 70.577 MHz 14.169 13006.664
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,3) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 0.875
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 3.724
macrocell23 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 3.465
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 70.592 MHz 14.166 13006.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,3) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 0.875
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 3.721
macrocell23 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 2.345
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 3.465
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 3.760
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 71.174 MHz 14.050 13006.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,2) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 0.875
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 5.251
macrocell21 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 2.345
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.229
statusicell1 U(3,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.350
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 72.459 MHz 13.801 13007.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 0.875
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 5.002
macrocell21 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 2.345
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.229
statusicell1 U(3,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.350
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 73.089 MHz 13.682 13007.151
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 2.510
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 3.248
macrocell21 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 2.345
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.229
statusicell1 U(3,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.350
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 76.028 MHz 13.153 13007.680
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,2) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 0.875
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.501
macrocell20 U(3,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 2.345
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.102
datapathcell2 U(3,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 4.330
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 77.214 MHz 12.951 13007.882
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 0.875
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.299
macrocell20 U(3,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 2.345
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.102
datapathcell2 U(3,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 4.330
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxSts\/status_0 78.125 MHz 12.800 13008.033
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 0.875
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_status_0\/main_1 4.001
macrocell21 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_1 \UART_1:BUART:tx_status_0\/q 2.345
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.229
statusicell1 U(3,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.350
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_0\/main_10 3.088
macrocell33 U(2,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_state_2\/main_9 3.088
macrocell36 U(2,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_last\/main_0 3.088
macrocell42 U(2,5) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_1\/main_4 3.542
macrocell39 U(2,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:pollcount_0\/main_3 3.542
macrocell40 U(2,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 6.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_status_3\/main_7 5.885
macrocell41 U(2,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)_SYNC/out \UART_1:BUART:sRX:RxShifter:u0\/route_si 8.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 Rx_1(0)_SYNC Rx_1(0)_SYNC/clock Rx_1(0)_SYNC/out 0.250
Route 1 Net_277_SYNCOUT Rx_1(0)_SYNC/out \UART_1:BUART:rx_postpoll\/main_2 3.542
macrocell24 U(2,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 2.345
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.114
datapathcell3 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(2,3) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 0.875
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.693
statusicell2 U(2,2) 1 \UART_1:BUART:sRX:RxSts\ HOLD -1.400
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 2.528
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.130
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 2.398
macrocell29 U(3,1) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.430
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.110
macrocell39 U(2,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 2.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.430
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_0\/main_0 2.110
macrocell40 U(2,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.430
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.409
macrocell34 U(3,5) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_7 2.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.430
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_7 2.415
macrocell33 U(2,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 2.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.430
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 2.415
macrocell36 U(2,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.430
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.449
macrocell39 U(2,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 2.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.430
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_0\/main_1 2.449
macrocell40 U(2,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_6 2.894
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,0) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 0.875
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_6 2.019
macrocell27 U(3,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\DataOut:Sync:ctrl_reg\/control_0 DB(0)_PAD:out 23.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_241_0 \DataOut:Sync:ctrl_reg\/control_0 DB(0)/pin_input 6.442
iocell8 P15[3] 1 DB(0) DB(0)/pin_input DB(0)/pad_out 15.486
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_7 DB(7)_PAD:out 22.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_7 1.435
Route 1 Net_241_7 \DataOut:Sync:ctrl_reg\/control_7 DB(7)/pin_input 6.129
iocell15 P3[4] 1 DB(7) DB(7)/pin_input DB(7)/pad_out 14.987
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_1 DB(1)_PAD:out 22.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_1 1.435
Route 1 Net_241_1 \DataOut:Sync:ctrl_reg\/control_1 DB(1)/pin_input 5.736
iocell9 P15[2] 1 DB(1) DB(1)/pin_input DB(1)/pad_out 15.104
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_5 DB(5)_PAD:out 22.175
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_5 1.435
Route 1 Net_241_5 \DataOut:Sync:ctrl_reg\/control_5 DB(5)/pin_input 6.149
iocell13 P3[6] 1 DB(5) DB(5)/pin_input DB(5)/pad_out 14.591
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_6 DB(6)_PAD:out 22.105
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_6 1.435
Route 1 Net_241_6 \DataOut:Sync:ctrl_reg\/control_6 DB(6)/pin_input 5.332
iocell14 P3[5] 1 DB(6) DB(6)/pin_input DB(6)/pad_out 15.338
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_3 DB(3)_PAD:out 21.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_3 1.435
Route 1 Net_241_3 \DataOut:Sync:ctrl_reg\/control_3 DB(3)/pin_input 6.275
iocell11 P15[0] 1 DB(3) DB(3)/pin_input DB(3)/pad_out 14.255
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_4 DB(4)_PAD:out 21.952
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_4 1.435
Route 1 Net_241_4 \DataOut:Sync:ctrl_reg\/control_4 DB(4)/pin_input 5.356
iocell12 P3[7] 1 DB(4) DB(4)/pin_input DB(4)/pad_out 15.161
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
\DataOut:Sync:ctrl_reg\/control_2 DB(2)_PAD:out 21.519
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \DataOut:Sync:ctrl_reg\ \DataOut:Sync:ctrl_reg\/busclk \DataOut:Sync:ctrl_reg\/control_2 1.435
Route 1 Net_241_2 \DataOut:Sync:ctrl_reg\/control_2 DB(2)/pin_input 5.655
iocell10 P15[1] 1 DB(2) DB(2)/pin_input DB(2)/pad_out 14.429
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000
+ UART_1_Clock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 30.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 0.875
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_273/main_0 2.340
macrocell19 U(2,0) 1 Net_273 Net_273/main_0 Net_273/q 2.345
Route 1 Net_273 Net_273/q Tx_1(0)/pin_input 9.514
iocell17 P2[0] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.667
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock To Output Enable Section
+ CyBUS_CLK
Source Destination Type Delay (ns)
CS(0)_SYNC/out DB(6)_PAD:out TURN ON 31.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(6)/oe 7.972
iocell14 P3[5] 1 DB(6) DB(6)/oe DB(6)/pad_out 17.787
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(6)_PAD:out TURN OFF 31.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(6)/oe 7.972
iocell14 P3[5] 1 DB(6) DB(6)/oe DB(6)/pad_out 17.787
Route 1 DB(6)_PAD DB(6)/pad_out DB(6)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(4)_PAD:out TURN ON 31.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(4)/oe 7.972
iocell12 P3[7] 1 DB(4) DB(4)/oe DB(4)/pad_out 17.319
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(4)_PAD:out TURN OFF 31.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(4)/oe 7.972
iocell12 P3[7] 1 DB(4) DB(4)/oe DB(4)/pad_out 17.319
Route 1 DB(4)_PAD DB(4)/pad_out DB(4)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(5)_PAD:out TURN ON 31.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(5)/oe 7.972
iocell13 P3[6] 1 DB(5) DB(5)/oe DB(5)/pad_out 17.282
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(5)_PAD:out TURN OFF 31.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(5)/oe 7.972
iocell13 P3[6] 1 DB(5) DB(5)/oe DB(5)/pad_out 17.282
Route 1 DB(5)_PAD DB(5)/pad_out DB(5)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(7)_PAD:out TURN ON 30.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(7)/oe 7.972
iocell15 P3[4] 1 DB(7) DB(7)/oe DB(7)/pad_out 16.646
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(7)_PAD:out TURN OFF 30.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(7)/oe 7.972
iocell15 P3[4] 1 DB(7) DB(7)/oe DB(7)/pad_out 16.646
Route 1 DB(7)_PAD DB(7)/pad_out DB(7)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(0)_PAD:out TURN ON 30.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(0)/oe 6.110
iocell8 P15[3] 1 DB(0) DB(0)/oe DB(0)/pad_out 17.921
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(0)_PAD:out TURN OFF 30.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(0)/oe 6.110
iocell8 P15[3] 1 DB(0) DB(0)/oe DB(0)/pad_out 17.921
Route 1 DB(0)_PAD DB(0)/pad_out DB(0)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(3)_PAD:out TURN ON 30.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(3)/oe 6.110
iocell11 P15[0] 1 DB(3) DB(3)/oe DB(3)/pad_out 17.880
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(3)_PAD:out TURN OFF 30.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(3)/oe 6.110
iocell11 P15[0] 1 DB(3) DB(3)/oe DB(3)/pad_out 17.880
Route 1 DB(3)_PAD DB(3)/pad_out DB(3)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(1)_PAD:out TURN ON 29.689
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(1)/oe 6.110
iocell9 P15[2] 1 DB(1) DB(1)/oe DB(1)/pad_out 17.490
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(1)_PAD:out TURN OFF 29.689
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(1)/oe 6.110
iocell9 P15[2] 1 DB(1) DB(1)/oe DB(1)/pad_out 17.490
Route 1 DB(1)_PAD DB(1)/pad_out DB(1)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(2)_PAD:out TURN ON 29.362
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(2)/oe 6.110
iocell10 P15[1] 1 DB(2) DB(2)/oe DB(2)/pad_out 17.163
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000
CS(0)_SYNC/out DB(2)_PAD:out TURN OFF 29.362
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 CS(0)_SYNC CS(0)_SYNC/clock CS(0)_SYNC/out 0.710
Route 1 Net_436_SYNCOUT CS(0)_SYNC/out OE/main_0 3.034
macrocell2 U(2,2) 1 OE OE/main_0 OE/q 2.345
Route 1 OE OE/q DB(2)/oe 6.110
iocell10 P15[1] 1 DB(2) DB(2)/oe DB(2)/pad_out 17.163
Route 1 DB(2)_PAD DB(2)/pad_out DB(2)_PAD:out 0.000
Clock Clock path delay 0.000